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-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:00:27 11/23/2017 
-- Design Name: 
-- Module Name:    fdiv100hz - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fdiv100hz is
    Port ( clk : in  STD_LOGIC;
           clko : out  STD_LOGIC);
end fdiv100hz;

architecture Behavioral of fdiv100hz is
signal clk_o:STD_LOGIC:='0';
signal cnt:integer range 0 to 240000:=1;
begin

process(clk)
begin
if clk'event and clk='1' then
   if cnt = 240000 then
    clk_o <= not clk_o ;
      cnt<=1;
      else
      cnt<=cnt+1;
      end if;
     clko<= clk_o;
end if;
end process;
end Behavioral;